The present invention relates to a method of calculating the total source/drain resistance for a field effect transistor (FET) device with multiple contacts in a single source/drain region, and more specifically, it relates to a method of extracting and netlisting multiple diffusion resistance elements, multiple contact resistance elements, and multiple segments of wire resistance elements for a FET device with multiple contacts in a single source/drain region.
When a source/drain region of a FET device (or a bi-polar device or a metal oxide semiconductor varactor) is contacted by multiple contacts, there exists a need to calculate or extract total source/drain resistance of the FET device. In this patent, when we say total source resistance, it includes diffusion resistances, contact resistances, and wire resistances at a FET's source side. Similarly, in this patent, when we say total drain resistance, it includes diffusion resistance, contact resistance, and wire resistance at a FET's drain side. Using conventional calculation or extraction methods, however, it is difficult to correctly calculate or correctly extract and netlist the total source/drain resistance coming from multiple diffusion resistance elements, multiple contact resistance elements, and multiple segments of wire resistance elements.